1. Technical Field
This invention relates generally to integrated memory cells and, more particularly, to a "zener-zap" memory cell with pretest capability for testing effects of the memory cell prior to permanently programming the memory cell by electrically overstressing a memory element.
2. Discussion
Bipolar integrated circuits commonly employ electrically overstressed reversed biased P.backslash.N+ junctions operated in the avalanche region as a means for providing nonvolatile memory.-This type of programming commonly employs permanently overstressed zener diodes as memory elements and is generally referred to as "zener-zap" programming. Typically, "zener-zap" memory cells include zener diodes as memory elements and are employed in a memory array for providing a plurality of memory bits. In order to program each of the zener diodes, a programming voltage which exceeds the reverse breakdown voltage of the zener diodes is coupled to each memory cell via separate interconnections for electrically overstressing each zener diode. Therefore, if the number of bits to be programmed is large, a similarly large number of interconnections are typically required. Because "zener-zap" programming is irreversible, these interconnections become of no further value once the respective zener diodes are programmed.
Thus, it would be desirable to reduce the number of interconnections required for programming individual "zener-zap" memory cells within a memory array. Furthermore, due to the irreversibility of "zener-zap" programming, it would be desirable to provide a "zener-zap" memory cell with the capability of generating a programmed output signal without irreversibly electrically overstressing the memory cell's zener diode. Such a capability would provide flexibly for testing the effects that permanently programming the memory cell would have on a circuit receiving the programmed output signal.
One of the objects of the present invention is to provide a "zener-zap" memory cell and method that advantageously allows the effects of programming the memory cell to be non-destructively tested prior to permanently programming the memory cell.
Another object of this invention is to provide a "zener-zap" memory array and method that allows a plurality of "zener-zap" memory cells to be individually non-destructively tested and individually permanently programmed with a minimum number of interconnections.